TSMC 기술 컨퍼런스 2022의 3가지 핵심 학습

In 2015, it was certified by InFo, a state-of-the-art 3DIC packaging technology.
TSMC made its most advanced logic technology (N7) available to everyone in 2018.
TSMC’s N5 EUV-based logic technology sets the standard in 2020.
TSMC introduced the N4P, N4X and N6RF in 2021.
The newest N3 process node serving a wide range of vertical sectors will be introduced by TSMC in 2022. In my judgment, N3 will surpass the previous high of tapeout over a five-year period.
In particular, TSMC unveiled next-generation process technology for the general public in 2022.

TSMC will continue to invest in mature nodes and expertise (Kumamoto Japan) with a 1.5x capacity increase from 2021 to 2025, including Fabs F14P8 (Tianan), F16P1B (Nanjing), F22P2 (Kaohsiung) and Fab F23P1.
TSMC also unveiled integrated specialty technology platforms for NVM, HV, sensor, PMIC, ULP/ULL, analog and RF technologies. I’m going to tell you more about Tom Dillinger here.

N3 scaling will continue at TSMC. HVM for N3 is expected in the second quarter of 2022. N3E with improved performance/power and less process complexity in both mobile and HPC applications will follow in Q2 2023.
The performance difference between N3EPA and N5 is 18% speed at the same power or 34% power reduction at the same speed, with a 1.6x improvement in logic density.
Even more important is FinFlex: Ultimate Design Flexibility for N3, announced by TSMC. TSMC’s latest FinFlex blog post provides more information. Be careful because Tom Dillinger will also be involved in this.

For the N2, TSMC will use nanosheet transistors. That’s not too surprising given that Intel and Samsung have already issued statements, but there’s a lot more going on here. N2 PPA versus N3E is expected to increase speed by 15% at the same power, or increase power by 25-30% at the same speed and increase density by a factor of >1.1. N2 will arrive around 2025.
TSMC also looked at the future of device architectures, including nanosheets, CFETs, 2D TMDs, and CNTs, which we’ll get into more about later.

Ultimately, everyone should keep in mind that a PurePlay foundry is quite different from an IDM foundry. With a fully supported ecosystem for hundreds of products, the most versatile and cost-effective process technology has to be produced by TSMC.
IDM foundries are free to prioritize and are not constrained by wafer margin requirements. Insiders in the semiconductor industry know this, but not in the press, so expect more false information in the future.In 2015, it was certified by InFo, a state-of-the-art 3DIC packaging technology.
TSMC made its most advanced logic technology (N7) available to everyone in 2018.
TSMC’s N5 EUV-based logic technology sets the standard in 2020.
TSMC introduced the N4P, N4X and N6RF in 2021.
The newest N3 process node serving a wide range of vertical sectors will be introduced by TSMC in 2022. In my judgment, N3 will surpass the previous high of tapeout over a five-year period.
In particular, TSMC unveiled next-generation process technology for the general public in 2022.

TSMC will continue to invest in mature nodes and expertise (Kumamoto Japan) with a 1.5x capacity increase from 2021 to 2025, including Fabs F14P8 (Tianan), F16P1B (Nanjing), F22P2 (Kaohsiung) and Fab F23P1.
TSMC also unveiled integrated specialty technology platforms for NVM, HV, sensor, PMIC, ULP/ULL, analog and RF technologies. I’m going to tell you more about Tom Dillinger here.

N3 scaling will continue at TSMC. HVM for N3 is expected in the second quarter of 2022. N3E with improved performance/power and less process complexity in both mobile and HPC applications will follow in Q2 2023.
The performance difference between N3EPA and N5 is 18% speed at the same power or 34% power reduction at the same speed, with a 1.6x improvement in logic density.
Even more important is FinFlex: Ultimate Design Flexibility for N3, announced by TSMC. TSMC’s latest FinFlex blog post provides more information. Be careful because Tom Dillinger will also be involved in this.

For the N2, TSMC will use nanosheet transistors. That’s not too surprising given that Intel and Samsung have already issued statements, but there’s a lot more going on here. N2 PPA versus N3E is expected to increase speed by 15% at the same power, or increase power by 25-30% at the same speed and increase density by a factor of >1.1. N2 will arrive around 2025.
TSMC also looked at the future of device architectures, including nanosheets, CFETs, 2D TMDs, and CNTs, which we’ll get into more about later.

Ultimately, everyone should keep in mind that a PurePlay foundry is quite different from an IDM foundry. With a fully supported ecosystem for hundreds of products, the most versatile and cost-effective process technology has to be produced by TSMC.
IDM foundries are free to prioritize and are not constrained by wafer margin requirements. Insiders in the semiconductor industry know this, but not in the press, so expect more false information in the future.